ELA is an exciting, fast-paced company that is focused on a high-growth segment of the electronic chip design market. We are an extremely motivated and talented team of professionals that work directly with our customers to ensure they can successfully build their next SoC design.

We are looking for Design For Test (DFT) engineers with strong communication skills, have a self starting attitude, play well in a team environment, and have multiple ASIC/COT project completion experiences under their belt.

ELA's design center is located in Pleasanton, CA. We are looking to fulfill any of these positions in Pleasanton or the greater San Francisco Bay area. All these positions are senior positions and require at least 15 years of experience and with appropriate degrees (BS in EE required, MS in EE preferred).

DFT Engineers

You will develop test specifications and implementation strategies and then be responsible for the test logic insertion including JTAG, boundary scan, memory BIST, scan and logic BIST. You will use STA to identify critical test paths and logic areas. After running vector generation, simulation and qualification you will help bring up the test program on the ATE. Yield data analysis will also play a large part in this job to improve our customer’s bottom line.

Required skills for this position include:

• Deep understanding of SCAN-based test methodologies including speed defect delay testing, bridge fault testing, etc.;
• Deep understanding of JTAG test methods including 1149.1 & 1149.6;
• Deep understanding of MEMORY BIST test methods for embedded emories;
• Deep understanding of test methods for embedded IP cores;
• Expert working knowledge of standard test tools and flows;
• Ability to automate the design flow via shell scripts, perl scripts, etc.;
• Completion of at least 10 projects through ramp to production;